The packaging of electronic devices is becoming more important as demands increase for miniaturization, speed, improved reliability, weight reduction and security. A variety packages are under development such as a die-scale package, at a wafer level; and a die stack-type package. Die have been attached to an interposer to mount the die onto a printed circuit board (PCB) through an organic package substrate to translate the fine geometries of the interposer to the much larger spacing of the printed circuit board. An increasing number of conductive pads of the printed circuit board must be coordinated with more bonding pads on the semiconductor die to improve input/output (I/O) throughput.
As Moore's law approaches its decrescendo and the cost per transistor increases below the 22 nm node, device makers are seeking alternative solutions to stay competitive. Semiconductor device manufacturers have been relying on Multi-Chip-Module (MCM) 100 shown in FIGS. 1A and 1B. 2D monolithic dies (120, 130) are integrated on an organic substrate 160 assembled on a Printed Circuit Board (PCB) 110. 2D monolithic dies 120 may be flip chip dies mechanically and electrically connected to organic substrate 160 by way of solder bumps 140. Alternatively, 2D monolithic dies 130 may be electrically connected to organic substrate 160 by way of wirebonds 131. Ball Grid Array (BGA) 150 may be used to connect organic substrate 160 to PCB 110. This approach results in a relatively low yield due to the increase in substrate size which causes mechanical stresses and other yield killing effects.
These shortcomings were partially addressed by moving to a Package-on-Package (POP) architecture as shown in FIGS. 2A and 2B. A Package-on-Package architecture may possess a vertical stacking of one monolithic die 201 above a second monolithic die 202 in the depicted manner. Monolithic die 201 and monolithic die 202 each have their own organic substrate (231 and 232, respectively). Monolithic die 201 is individually packaged on organic substrate 231 using solder balls 221 whereas monolithic die 202 is individually packaged onto organic substrate 232 using solder balls 222. Clearance is provided for monolithic die 202 by incorporating organic substrates 210 which may provide electrical connections between organic substrate 231 and organic substrate 232 through additional solder balls 220. Practical considerations (e.g. reliability and maintaining a low profile) limit the number of levels which can be implemented in this Package-on-Package architecture. A perspective view is provided in FIG. 2B to help visualize the completed package in three dimensions. The size of the solder bumps may be increased and provide the clearance for monolithic die 202 which does indeed lower the profile, however, the technique also reduces the number of electrical connections which may be made between organic substrate 231 and organic substrate 232.
More recently, “2.5D” and “3D” integration techniques have been developed to improve yield, profile and performance. 2.5D/3D approaches may also increase the reuse of monolithic integrated circuit (“chip”) designs whose development costs have already been amortized. Various chip designs (often referred to as IP) perhaps from differing process nodes and perhaps from different foundries can be integrated together to form a functional circuit device. In a homogeneous 2.5D/3D integration approach, as illustrated in FIG. 3A, a single chip 300 is partitioned into number of smaller chips (305, 310, 315, 320). Smaller chips (305, 310, 315, 320) are then assembled onto interposer 325 and wired together to form an electronic package. FIG. 3B shows a heterogeneous 2.5D/3D integration approach. Single chip 330 includes a number of circuitry blocks including memory 335, logic 340, DSP 345, and RF 350 manufactured separately and mounted on interposer 355 and wired together to form an electronic package. Smaller chips (335, 340, 345, 350) may be manufactured by different foundries and may have different process nodes selected for performance, availability and/or cost reasons.
Hardware is needed which further increase the number of transistors per device to improve processing performance and/or lower the cost per transistor.